Cypress Introduces New Development Platform for PSoC 5 Programmable System-on-Chip Architecture with ARM Cortex-M3 Processor

New Scalable Platform Combines Programmable Precision Analog and Digital Logic with High Performance 32-Bit Processor for Unmatched Integration, and Flexibility

• Two new development kits for PSoC 5 Architecture
• Samples now available for PSoC 5 CY8C55xxx family
• Enhanced version of PSoC Creator Software IDE with PSoC5 support

Cypress introduced the new development platform for the revolutionary PSoC® 5 programmable system-on-chip architecture. The company unveiled two new design kits, a new version of the PSoC Creator Integrated Development Environment (IDE), and announced that devices from the CY8C55xxx family are now sampling.  The unique programmable analog and digital peripherals in PSoC 5, along with the high performance 32-bit ARM® Cortex™-M3 processor, position PSoC5 for demanding applications such as industrial, medical, automotive, and consumer equipment. PSoC 5 devices offer industry-leading integrated analog resources, including one 20-bit Delta Sigma ADC and two 12-bit SAR ADCs with sample rates as high as 1 Msps. 

NXP announces the LPC11C22 and LPC11C24, entry level 32-bit MCUs with integrated CAN transceiver in a multi-chip solution. 

NXP launches industry's first Integrated MCU and CAN transceiver with high-speed CAN Physical Layer transceiver. The LPC11C2x is a multichip solution which integrates NXP's TJF1051 CAN transceiver with an ARM Cortex-M0, an ADC, SPI, UART, I2C and 32KB of Flash combined with 8K SRAM. Industrial and automation market is the primary target for this chip

While some CAN transceivers can cost as much as or even more than the microcontroller itself, NXP believes its multichip solution will only carry a 20% premium over the price of the microcontroller alone. Integrating the CAN transceiver on board also increases system reliability and quality, according to the company, while reducing electrical interconnect and compatibility issues, and reduces board space by over 50%.

The CAN Physical Layer is designed for up to 1 Mbit/s High-Speed CAN networks and delivers optimal performance for industrial applications with state-of-the-art Electrostatic Discharge (ESD) protection, improved Electromagnetic Compatibility (EMC) and low power operation.

The LPC11C22/C24 CAN Physical Layer is fully compliant with the ISO 11898-2 standard for two-wire balanced signaling and is optimised for automotive sensor applications and rugged industrial CAN networks.

As with the existing family without the integrated transceiver, CANopen drivers are provided in on-chip ROM with easy-to-use APIs. This standardised CANopen layer (EN 50325) is especially well suited for embedded networks in all kinds of control, such as machines and elevators, making proprietary or application-specific application layers obsolete.

Incorporating CANopen drivers in on-chip ROM reduces overall risk and effort while providing design engineers with the added advantage of reduced operating power, as well as secure and safe bootloading via CAN. With the security and peace of mind offered by ROM-based drivers, updating Flash via In System Programming (ISP) over the CAN-bus provides the whole range of functionality – from programming blank parts in production, through changing system parameters, to full in-field re-programmability.