The LPC1800 is optimized for fast operation all the way through to 150 MHz maximum performance from either Flash or RAM. NXP has re-introduced the double flash bank technology that is a proven concept to speed up execution from flash beyond the possibilities given with one 128-bit wide bank. If the user selects to option to write to one bank while executing from the other flash bank, there might be some speed penalty but the write while execute feature is well worth that. Overall the feature list, which includes dual HS-USB, 10/100 Ethernet and AES decryption, optional also AES encryption and a high-resolution LCD controller reads like a wish list for many designers in the communication space.

NXP’s ultra low-leakage 90 nm process technology offers faster operation, low dynamic power consumption. The LPC1800 offers the industry’s largest on-chip SRAM for a Cortex-M3 with up to 200 KB provided in multiple banks, each with separate bus master access for higher throughput and individual power-down control for low power operation. The drawback of this approach is that an OS will have to deal with multiple banks too, reducing its efficiency.

Additional peripherals available on the LPC1800 include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware enabled TCP/IP checksum calculation, a high-resolution color LCD controller in the 180- and 256-BGA, and AES decryption including two 128-bit secure OTP memories for key storage. Versions with AES encryption are available on request.
 
Standard features on all members of the series include 32 KB ROM containing boot code and on-chip software drivers, eight-channel General-Purpose DMA controller, two 10-bit ADCs and 10-bit DAC with data conversion rate of 400k samples/s, a motor Control PWM and Quadrature Encoder Interface, 4 UARTs, 2 Fast-mode Plus I2C, I2S, 2 SSP/SPI, CAN, Smart card interface, 4 timers, windowed watchdog timer, an alarm timer, an ultra-low power RTC with 256 bytes of battery powered backup registers found its way back into the system after being omitted on the LPC1700 and up to 80 general purpose I/O pins.

The LPC1800 also features two new innovative peripherals: a flexible quad-SPI interface and a state configurable timer subsystem. Taking advantage of the rapid adoption of quad-SPI architectures in newer serial Flash memories, NXP is the first to provide a seamless high-speed interface that will connect with virtually all SPI and quad-SPI manufacturers. High-speed interfacing from quad-lane SPI memories at up to 80 Mbps per lane provides for much larger off-chip data and code execution than available from on-chip memories.

The LPC1800‘s State Configurable Timer Subsystem comprises of a timer array with a state machine enabling complex functionality including event controlled PWM waveform generation, ADC synchronization and dead time control. This timer subsystem gives embedded designers increased flexibility to create user-defined wave-forms and control signals for many applications including power conversion, lighting and motor applications.

For those of you wondering why NXP went back to a lower performance ADC, it is the new 90 nm process that is responsible for it. It always takes a little longer to create good analog components in a new process. Some of you might think 90 nm, a new process? Well yes, 90 nm Flash, low leakage process is fairly new.

For those user who would like to upgrade from the LPC1700 to LPC1800 for larger flash, larger SRAM and higher speed, hope you are not depending on the 12-bit ADC.There is a very preliminary data sheet available on the NXP website

Availability and pricing

The LPC1800 is available in 144-pin and 208-pin LQFP packages and 100-pin, 180-pin and 256-pin BGA packages. Usually NXP is very open with pricing, this time the announcement was not accompanied by pricing information. Flash-based LPC1800 engineering samples are available now. Flashless LPC18x0 parts, featuring larger on-chip SRAM, are sampling now and will be available through distribution in December 2010.