MCU related information at your fingertips

Home

Main Menu

Development Tools

Professional development tools can save you lots of money

Working with professional tools can make the difference between a project succeeding or failing. Why are GNU tools not part of my category professional tools?

1. The possible optimization for code size has improved steadily over the years but compilers from IAR or ARM are still better. If this is important for you, I can't tell but telling from experience, there will always be that one extra feature requested from a customer and if you are using GNU tools, there will be this one feature less fitting in the memory, provided both programmers are equally smart. If you are using external memory this difference is usually void, if everything has to fit in an internal Flash memory the small difference can be worth a lot.

2. Optimization for speed is something that can be seen when processor vendors are running industry benchmarks such as EEMBC benchmarks. In the past most benchmarks used the Greenhills compiler because it offered the speed speed optimization. IAR managed to pull off a tie with EWARM 6.40 and the latest announcement for EWARM 6.50 talks about another 10% or more improvement in industry benchmarks. This will put IAR in the lead for speed optimization.

3. Optimization for Power is a relatively new concept. IAR offers Power Debugging and provides information to the software developer how a specific implementation affects power consumption.

4. Code Debugging with GDB or a real debugger. Each debugger is only as good as the engineer is familiar with it. All other things equal, commercial debuggers such as uVision or C-SPY offer lots of additional functionality over GDB.

These professional tools might be not be an option for hobbyists but as a company which depends on revenue from a product the question is: Can you afford NOT to use such professional tools?

The answer is up to you!

Last Updated on Monday, 19 November 2012 06:49

PSoC 5 CY8C55

Cypress Introduces New Development Platforms for PSoC 5 Programmable System-on-Chip Architecture with ARM Cortex-M3 Processor

New Scalable Platform Combines Programmable Precision Analog and Digital Logic with High Performance 32-Bit Processor for Unmatched Integration and Flexibility

• Two new development kits for PSoC 5 Architecture
• Samples now available for PSoC 5 CY8C55xxx family
• Enhanced version of PSoC Creator the software IDE with PSoC5 support

Cypress introduced the new development platform for the revolutionary PSoC® 5 programmable system-on-chip architecture. The company unveiled two new design kits, a new version of the PSoC Creator Integrated Development Environment (IDE), and announced that devices from the CY8C55xxx family are now sampling. The unique programmable analog and digital peripherals in PSoC 5, along with the high performance 32-bit ARM® Cortex™-M3 processor, position PSoC5 for demanding applications such as industrial, medical, automotive, and consumer equipment. PSoC 5 devices offer industry-leading integrated analog resources, including OpAmps, comparators, DACs, a 20-bit Delta Sigma ADC and two 12-bit SAR ADCs with sample rates up to 700 KS/sec.

Last Updated on Wednesday, 26 September 2012 21:31

STM32F200 on the ST roadmap

ST is preparing some major new families using the Cortex-M3 for release in 2010. Based on publicly available information*, there will be a STMF200 family, a STMF150 family and a STM32F100 family. Top of the line the STM32F200 STM32 Plus! with 120MHz devices, featuring USB OTG and Ethernet, most likely with 1 MB of on-chip flash.
Last Updated on Sunday, 07 February 2010 19:59
Read more...

LPC11C24 MCU with CAN transceiver

NXP announces the LPC11C22 and LPC11C24, entry level 32-bit MCUs with integrated CAN transceiver in a multi-chip solution.

NXP launches industry's first Integrated MCU and CAN transceiver with high-speed CAN Physical Layer transceiver. The LPC11C2x is a multichip solution which integrates NXP's TJF1051 CAN transceiver with an ARM Cortex-M0, an ADC, SPI, UART, I2C and 32KB of Flash combined with 8K SRAM. Industrial and automation market is the primary target for this chip

While some CAN transceivers can cost as much as or even more than the microcontroller itself, NXP believes its multichip solution will only carry a 20% premium over the price of the microcontroller alone. Integrating the CAN transceiver on board also increases system reliability and quality, according to the company, while reducing electrical interconnect and compatibility issues, and reduces board space by over 50%.

The CAN Physical Layer is designed for up to 1 Mbit/s High-Speed CAN networks and delivers optimal performance for industrial applications with state-of-the-art Electrostatic Discharge (ESD) protection, improved Electromagnetic Compatibility (EMC) and low power operation.

The LPC11C22/C24 CAN Physical Layer is fully compliant with the ISO 11898-2 standard for two-wire balanced signaling and is optimised for automotive sensor applications and rugged industrial CAN networks.

As with the existing family without the integrated transceiver, CANopen drivers are provided in on-chip ROM with easy-to-use APIs. This standardised CANopen layer (EN 50325) is especially well suited for embedded networks in all kinds of control, such as machines and elevators, making proprietary or application-specific application layers obsolete.

Incorporating CANopen drivers in on-chip ROM reduces overall risk and effort while providing design engineers with the added advantage of reduced operating power, as well as secure and safe bootloading via CAN. With the security and peace of mind offered by ROM-based drivers, updating Flash via In System Programming (ISP) over the CAN-bus provides the whole range of functionality – from programming blank parts in production, through changing system parameters, to full in-field re-programmability.

LPC1800 the fastest Cortex-M3

The LPC1800 is optimized for fast operation all the way through to 150 MHz maximum performance from either Flash or RAM. NXP has re-introduced the double flash bank technology that is a proven concept to speed up execution from flash beyond the possibilities given with one 128-bit wide bank. If the user selects to option to write to one bank while executing from the other flash bank, there might be some speed penalty but the write while execute feature is well worth that. Overall the feature list, which includes dual HS-USB, 10/100 Ethernet and AES decryption, optional also AES encryption and a high-resolution LCD controller reads like a wish list for many designers in the communication space.

NXP’s ultra low-leakage 90 nm process technology offers faster operation, low dynamic power consumption. The LPC1800 offers the industry’s largest on-chip SRAM for a Cortex-M3 with up to 200 KB provided in multiple banks, each with separate bus master access for higher throughput and individual power-down control for low power operation. The drawback of this approach is that an OS will have to deal with multiple banks too, reducing its efficiency.

Additional peripherals available on the LPC1800 include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware enabled TCP/IP checksum calculation, a high-resolution color LCD controller in the 180- and 256-BGA, and AES decryption including two 128-bit secure OTP memories for key storage. Versions with AES encryption are available on request.

Standard features on all members of the series include 32 KB ROM containing boot code and on-chip software drivers, eight-channel General-Purpose DMA controller, two 10-bit ADCs and 10-bit DAC with data conversion rate of 400k samples/s, a motor Control PWM and Quadrature Encoder Interface, 4 UARTs, 2 Fast-mode Plus I2C, I2S, 2 SSP/SPI, CAN, Smart card interface, 4 timers, windowed watchdog timer, an alarm timer, an ultra-low power RTC with 256 bytes of battery powered backup registers found its way back into the system after being omitted on the LPC1700 and up to 80 general purpose I/O pins.